Many CMOS integrated circuits utilize n.sup.+ gate material for both PMOS and NMOS devices. However, as gate lengths shrink, there is an increasing trend to the use of p.sup.+ gates for both PMOS and NMOS devices. P.sup.+ gate PMOS transistors (i.e., surface channel devices) exhibit good short channel performance, threshold voltages, and sub-threshold swings which are less dependent upon channel length than PMOS devices with n.sup.+ (i.e., buried channel devices) gates. P.sup.+ NMOS gate transistors have also been found satisfactory in various CMOS applications.
Typically, p.sup.+ gates are formed by depositing a polysilicon layer which is doped. The polysilicon is typically doped with boron or BF.sub.2. However, if the polysilicon is doped by ion implantation with boron, the dopant species (boron) may penetrate through the polysilicon (a phenomenon termed "channeling") into the substrate and cause changes in the threshold voltage. If the polysilicon is doped with BF.sub.2 (a larger species) channeling is less likely to occur. However, the presence of fluorine in the polysilicon seems to enhance boron diffusion through the gate oxide into the substrate during subsequent thermal treatments. Thus, the threshold voltage is again adversely affected.
N.sup.+ gates are typically formed from polysilicon doped with phosphorous. Since phosphorous atoms are bigger than boron atoms, channeling is a less serious problem for devices with n.sup.+ gates (assuming that the same thickness of polysilicon is employed).
One solution to the problem of channeling is to increase the thickness of the gate polysilicon material. (Gates with polysilicon thicknesses of roughly 3600 .ANG. often have acceptable resistance to channeling for currently-used implantation energies. However, such high gates create a topography which makes subsequent processing difficult.)
Some manufacturers of comparatively thin n.sup.+ gates cover the polysilicon with tungsten silicide and then with a silicon dioxide layer. The silicon dioxide layer is formed at a temperature high enough to cause crystallization of the tungsten silicide. After the silicon dioxide is formed, the gate is implanted with an n type dopant such as phosphorous.